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?2004 integrated device technology, inc. 1 october 2004 dsc 2943/6 i/o control address decoder memory array arbitration interrupt semaphore logic address decoder i/o control r/ w l ce l oe l busy l a 14l a 0l 2943 drw 01 i/o 0l -i/o 7l ce l oe l r/ w l sem l i nt l m/ s busy r i/o 0r -i/o 7r a 14r a 0r sem r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r 15 15 r/ w r , idt70v07s/l high-speed 3.3v 32k x 8 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location high-speed access ? commercial: 25/35/55ns (max.) ? industral: 25ns (max.) low-power operation ? idt70v07s active: 300mw (typ.) standby: 3.3mw (typ.) ? idt70v07l active: 300mw (typ.) standby: 660 w (typ.) interrupt flag idt70v07 easily expands data bus width to 16 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master m/ s = v il for busy input on slave on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port ttl-compatible, single 3.3v (0.3v) power supply available in 68-pin pga and plcc, and a 80-pin tqfp industrial temperature range (-40c to +85c) is available for selected speeds functional block diagram notes: 1. (master): busy is output; (slave): busy is input. 2. busy and int outputs are non-tri-stated push-pull.
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 2 2943 drw 02 12 13 14 15 16 17 18 index 19 20 21 22 98765432168676665 27 28 29 30 31 32 33 34 35 36 37 38 39 v c c v cc i/o 1r i/o 2r i/o 3r i/o 4r int l gnd a 4l a 3l a 2l a 1l a 0l a 3r a 0r a 1r a 2r i/o 2l a 5l 11 10 m/ s 23 24 25 26 40 41 42 43 58 57 56 55 54 53 52 51 50 49 48 59 60 47 46 45 44 64 63 62 61 i/o 3l gnd i/o 0r v cc a 4r busy l gnd busy r int r a 1 2 r i / o 7 r n / c g n d o e r r / w r c e r c e l n / c i / o 0 l i / o 1 l idt70v07j j68-1 (4) 68-pin plcc top view (5) i/o 4l i/o 5l i/o 6l i/o 7l i/o 5r i/o 6r a 1 2 l a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r a 1 1 l a 1 0 l a 9 l a 8 l a 7 l a 6 l a 1 3 r a 1 3 l a 1 4 l a 1 4 r r / w l o e l s e m l s e m r 10/25/01 description the idt70v07 is a high-speed 32k x 8 dual-port static ram. the idt70v07 is designed to be used as a stand-alone 256k-bit dual-port ram or as a combination master/slave dual-port ram for 16-bit- or-more word systems. using the idt master/slave dual-port ram approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 300mw of power. the idt70v07 is packaged in a ceramic 68-pin pga and plcc and a 80-pin thin quad flatpack (tqfp). pin configurations (1,2,3) notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground. 3. j68-1 package body is approximately .95 in x .95 in x .17 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
3 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges index i/o 2l v cc gnd gnd a 4r busy l busy r gnd m/ s o e l i / o 1 l r / w l c e l s e m l v c c o e r c e r r / w r s e m r a 1 2 r g n d i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l i/o 0r i/o 1r i/o 2r v cc i/o 3r i/o 4r i/o 5r i / o 7 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r a 3r a 2r a 1r a 0r a 0l a 1l a 2l a 3l a 4l a 6 l a 7 l a 8 l a 9 l a 1 0 l a 1 1 l a 1 2 l i / o 0 l 2943 drw 03 a 1 3 r a 1 3 l 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 56 55 54 53 52 51 50 47 48 49 32 31 30 29 28 27 26 25 24 23 22 21 63 62 61 64 33 34 35 36 37 38 39 40 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 n / c n / c a 1 4 l n / c n / c n / c n / c a 1 4 r n / c n / c 17 18 19 20 57 58 59 60 a 5l n/c int l int r n/c n/c n/c i/o 6r n/c n/c idt70v07pf pn80-1 (4) 80-pin tqfp top view (5) 10/25/01 notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground. 3. pn80-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3) (con't.)
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 4 notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground. 3. package body is approximately 1.18 in x 1.18 in x .16 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin names pin configurations (1,2,3) (con't.) left port right port names ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 14l a 0r - a 14r address i/o 0l - i/o 7l i/o 0r - i/o 7r data input/outp ut sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/ s master or slave select v cc power (3.3v) gnd ground (0v) 2943 tbl 01 2943 drw 04 51 50 48 46 44 42 40 38 36 53 55 57 59 61 63 65 67 68 66 13579 11 13 15 20 22 24 26 28 30 32 35 idt70v07g g68-1 (4) 68-pin pga top view (5) abcdefgh j k l 47 45 43 41 34 21 23 25 27 29 31 33 246810121416 18 19 17 56 58 60 62 64 11 10 09 08 07 06 05 04 03 02 01 52 54 49 39 37 a 5l int l sem l ce l v cc oe l r/ w l i/o 0l n/c gnd gnd i/o 0r v cc n/c oe r r/ w r sem r ce r gnd busy r busy l m/ s int r gnd a 1r index a 4l a 2l a 0l a 3r a 2r a 4r a 5r a 7r a 6r a 9r a 8r a 11r a 10r a 12r a 0r a 7l a 6l a 3l a 1l a 9l a 8l a 11l a 10l a 12l v cc i/o 2r i/o 3r i/o 5r i/o 6r i/o 1r i/o 4r i/o 7r i/o 1l i/o 2l i/o 4l i/o 7l i/o 3l i/o 5l i/o 6l a 13r a 13l a 14r a 14l , 10/25/01
5 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges truth table i: non-contention read/write control truth table ii: semaphore read/write control maximum operating temperature and supply voltage (1) absolute maximum ratings (1) capacitance (1) (t a = +25c, f = 1.0mhz) tqfp only recommended dc operating conditions (2) note: 1. a 0l ? a 14l a 0r ? a 14r notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 0.3v. 3. ambient temperature under bias. no ac conditions. chip deselected. notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 0.3v. notes: 1. this parameter is determined by device characterization but is not production tested. 2. c out also references c i / o . note: 1. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 7 ). these eight semaphores are addressed by a 0 -a 2 inputs (1) outputs mode ce r/ w oe sem i/o 0-7 h x x h high-z deselected: power-down llxhdata in write to memory lhlhdata out read memory x x h x high-z outputs disabled 2943 tbl 02 inputs (1) outputs mode ce r/ w oe sem i/o 0-7 hhl ldata out read data in semaphore flag h xldata in write i/o 0 into semaphore flag lxxl ____ not allowed 2943 tbl 03 symbol rating commercial & industrial unit v term (2) te rm i n al vo lta g e with respect to gnd -0.5 to +4.6 v t bias (3) temperature under bias -55 to +125 o c t stg storagetemperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 2943 tbl 04 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v3.3v + 0.3 industrial -40 o c to +85 o c0v3.3v + 0.3 2943 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc +0.3 (2 ) v v il input low voltage -0.3 (1 ) ____ 0.8 v 2943 tbl 06 symbol parameter conditions max. unit c in input capacitance v in = 0v 9 pf c out (2) output capacitance v out = 0v 10 pf 2943 tbl 07
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 6 dc electrical characteristics over the operating temperature and supply voltage range (1) (v cc = 3.3v 0.3v) notes: 1. 'x' in part number indicates power rating (s or l). 2. v cc = 3.3v, t a = +25c, and are not production tested. i ccdc = 80ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/ t rc, and using ?ac test conditions" of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 0.3v) note: 1. at v cc < 2.0v, input leakages are undefined. symbol parameter test conditions 70v07s 70v07l unit min. max. min. max. |i li | input leakage current (1 ) v cc = 3.6v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2943 tb l 0 8 70v07x25 com'l & ind 70v07x35 com'l only 70v07x55 com'l only symbol parameter test condition version typ. (2) max. typ. (2) max. typ. (2) max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled sem = v il f = f max (3) com'l s l 100 100 170 140 90 90 140 120 90 90 140 120 ma ind s l ____ 100 ____ 185 ____ ____ ____ ____ ____ ____ ____ ____ i sb1 standby current (both ports - ttl le ve l inputs) ce r = ce l = v ih sem r = sem l = v ih f = f max (3) com'l s l 14 12 30 24 12 10 30 24 12 10 30 24 ma ind s l ____ 12 ____ 50 ____ ____ ____ ____ ____ ____ ____ ____ i sb2 standby current (one port - ttl le ve l inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (3) sem r = sem l = v ih com'l s l 50 50 95 85 45 45 87 75 45 45 87 75 ma ind s l ____ 50 ____ 105 ____ ____ ____ ____ ____ ____ ____ ____ i sb3 full standby current (both ports - cmos le ve l inputs) both ports ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) sem r = sem l > v cc - 0.2v com'l s l 1.0 0.2 6 3 1.0 0.2 6 3 1.0 0.2 6 3 ma ind s l ____ 0.2 ____ 3 ____ ____ ____ ____ ____ ____ ____ ____ i sb4 full standby current (one port - cmos le ve l inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3) com'l s l 60 60 90 80 55 55 85 74 55 55 85 74 ma ind s l ____ 60 ____ 90 ____ ____ ____ ____ ____ ____ ____ ____ 2943 tbl 09
7 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges ac test conditions figure 1. ac output test load timing of power-up power-down notes: 1. transition is measured 0mv from low- or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . 4. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (4) ce 2943 drw 07 t pu i cc i sb t pd , input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns 1.5v 1.5v fi gures 1 and 2 2943 tbl 10 figure 2. output test load (for t lz , t hz , t wz , t ow ) * including scope and jig. 2943 drw 06 590 ? 30pf 435 ? 3.3v data out busy i nt 590 ? 5pf* 435 ? 3.3v data out 2943 drw 05 70v07x25 com'l & ind 70v07x35 com'l only 70v07x55 com'l only unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 25 ____ 35 ____ 55 ____ ns t aa address access time ____ 25 ____ 35 ____ 55 ns t ace chip enable access time (3) ____ 25 ____ 35 ____ 55 ns t aoe output enable access time ____ 15 ____ 20 ____ 30 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz outp ut lo w-z tim e (1,2) 3 ____ 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 15 ____ 20 ____ 25 ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 25 ____ 35 ____ 50 ns t sop semaphore flag update pulse (oe or sem )15 ____ 15 ____ 15 ____ ns t saa semaphore address access time ____ 35 ____ 45 ____ 65 ns 2943 tbl 1 1
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 8 waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first, ce or oe . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simul taneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . notes: 1. transition is measured 0mv from low or high impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage (5) t rc r/ w ce addr t aa oe 2943 drw 08 (4) t ace (4) t aoe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) symbol parameter 70v07x25 com'l & ind 70v07x35 com'l only 70v07x55 com'l only unit min. max. min. max. min. max. write cycle t wc write cycle time 25 ____ 35 ____ 55 ____ ns t ew chip enable to end-of-write (3) 20 ____ 30 ____ 45 ____ ns t aw address valid to end-of-write 20 ____ 30 ____ 45 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t wp write pulse width 20 ____ 25 ____ 40 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-o f-write 15 ____ 20 ____ 30 ____ ns t hz output high-z time (1,2) ____ 15 ____ 20 ____ 25 ns t dh data ho ld time (4) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 15 ____ 20 ____ 25 ns t ow output active from end-of-write (1,2,4) 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ ns 2943 tbl 12
9 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce controlled timing (1,5) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 2). 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the speci fied t wp . 9. to access sram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in ce or sem (6) (4) (4) (3) 2943 drw 09 (7) (9) (7) t lz , t hz (7) 2943 drw 10 t wc t as t wr t dw t dh address data in r/ w t aw t ew (3) (2) (6) ce or sem (9)
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 10 timing waveform of semaphore read after write timing, either side (1) notes: 1. d or = d ol = v il , ce r = ce l = v ih . 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a" . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w b or sem "b" going high. 4. if t sps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtai n the flag. notes: 1. ce = v ih for the duration of the above timing (both write and read cycle). 2. ?data out valid? represents all i/o's (i/o 0 -i/o 7 ) equal to the semaphore value. timing waveform of semaphore write contention (1,3,4) sem 2943 drw 11 t aw t ew t sop data 0 valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd t aoe t sop read cycle write cycle a 0 -a 2 oe valid (2) sem "a" 2943 drw 12 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2)
11 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges 2943 drw 13 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa ac electrical characteristics over the operating temperature and supply voltage range (6) timing waveform of write with port-to-port read and busy (2,4,5) notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. if m/ s = v il (slave), then busy is an input ( busy "a" = v ih and busy "b" = "don't care", for this example). 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy ". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 'x' in part numbers indicates power rating (s or l). 70v07x25 com'l & ind 70v07x35 com'l only 70v07x55 com'l only symbol parameter min. max. min. max. min. max. unit busy timing (m/ s = v ih ) t baa busy access time from address ____ 25 ____ 35 ____ 45 ns t bda busy disable time from address ____ 25 ____ 35 ____ 45 ns t bac busy access time from chip enable ____ 25 ____ 35 ____ 45 ns t bdc busy disable time from chip enable ____ 25 ____ 35 ____ 45 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 35 ____ 40 ____ 50 ns busy timing (m/ s - v il ) t wb busy input to write (4) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 20 ____ 25 ____ 25 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 55 ____ 65 ____ 85 ns t ddd write data valid to re ad data de lay (1) ____ 50 ____ 60 ____ 80 ns 2943 tbl 13
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 12 waveform of busy arbitration controlled by ce timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. waveform of busy arbitration cycle controlled by address match timing (1) timing waveform of write with busy notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 2943 drw 14 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (1) (2) 2943 drw 15 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 2943 drw 16 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n"
13 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges note: 1. 'x' in part number indicates power rating (s or l). waveform of interrupt timing (1) ac electrical characteristics over the operating temperature and supply voltage range (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. see interrupt truth table iii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 70v07x25 com'l & ind 70v07x35 com'l only 70v07x55 com'l only symbol parameter min. max. min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins inte rrup t set time ____ 25 ____ 30 ____ 40 ns t inr inte rrup t res et time ____ 30 ____ 35 ____ 45 ns 2043 tbl 14 2943 drw 17 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 2943 drw 18 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2)
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 14 truth table iv ? address busy arbitration notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt70v07 are push- pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. truth table v ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70v07. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 - i/o 7 ). these eight semaphores are addressed by a 0 -a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. truth table iii ? interrupt flag (1) notes: 1. assumes busy l = busy r =v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. left port right port function r/ w l ce l oe l a 14l -a 0l int l r/ w r ce r oe r a 14r -a 0r int r llx7fffxxxx x l (2) se t right int r flag xxx x xxll7fff h (3) re set right int r flag xxx x l (3) l l x 7ffe x set left int l flag xll7ffe h (2) xxxxxreset left int l flag 2943 tbl 15 inputs outputs function ce l ce r a 0l -a 14l a 0r -a 14r busy l (1 ) busy r (1 ) xxno matchhhnormal hxmatchhhnormal xhmatchhhnormal l l match (2) (2) write inhibit (3 ) 2943 tbl 16 functions d 0 - d 7 left d 0 - d 7 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 2943 tbl 17
15 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges functional description the idt70v07 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70v07 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7ffe (hex), where a write is defined as ce r = r/ w r = v il per truth table iii. the left port clears the interrupt through access of address location 7ffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag (int r ) is asserted when the left port writes to memory location 7fff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory 7fff location 7fff. the message (8 bits) at 7ffe or 7fff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7ffe and 7fff are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 70v07 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70v07 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt70v07 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt70v07 is an extremely fast dual-port 32k x 8 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port sram to claim a privilege over the other processor for functions defined by the system designer?s software. as an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port sram or any other shared resource. the dual-port sram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are pro- tected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port sram. these devices have an automatic power- down feature controlled by ce , the dual-port sram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table busy logic busy logic provides a hardware indication that both ports of the sram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the sram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be figure 3. busy and chip enable routing for both width and depth expansion with idt70v07 rams. 2943 drw 19 master dual port ram busy l busy r ce master dual port ram busy l busy r slave dual port ram busy l busy r slave dual port ram busy l busy r busy l busy r d e c o d e r ce ce ce ,
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 16 d 2943 drw 20 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read , i where ce and sem are both high. systems which can best use the idt70v07 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70v07's hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70v07 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are indepen- dent of the dual-port sram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70v07 in a separate memory space from the dual-port sram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thor- ough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the figure 4. idt70v07 semaphore logic semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side?s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see truth table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two sema- phore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side?s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side?s request latch. the second side?s flag will now stay low until its semaphore request latch
17 idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and c ommercial temperature ranges is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. using semaphores?some examples perhaps the simplest application of semaphores is their applica- tion as resource markers for the idt70v07?s dual-port sram. say the 32k x 8 sram was to be divided into two 16k x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indicator for the upper section of memory. to take a resource, in this example the lower 16k of dual-port sram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 16k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 16k blocks of dual-port sram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual-port sram or other shared resources into eight parts. sema- phores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was ?off-limits? to the cpu, both the cpu and the i/o devices could access their assigned portions of memory continu- ously without any wait states. semaphores are also useful in applications where no memory ?wait? state is available on one or both sides. once a semaphore handshake has been performed, both processors can access their assigned sram segments at full speed. another application is in the area of complex data structures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaran- teeing a consistent data structure.
idt70v07s/l high-speed 32k x 8 dual-port static ram industrial and commercial temperature ranges 18 ordering information note: 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. 2943 drw 21 a power 999 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) pf g j 80-pin tqfp (pn80-1) 68-pin pga (g68-1) 68-pin plcc (j68-1) 25 35 55 s l standard power low power xxxxx device type 256k (32k x 8) 3.3v dual-port ram 70v07 idt speed in nanoseconds commercial & industrial commercial only commercial only , the idt logo is a registered trademark of integrated device technology, inc. datasheet document history: 3/24/99: initiated datasheet document history converted to new format cosmetic and typographical corrections page 2 and 3 added additional notes to pin configurations 6/9/99: changed drawing format t 10/14/04: removed preliminary status page 1 added i-temp offering page 4 updated capacitance table increased storage temp parameter in absolute maximum rating table added junction temp to absolute maximum rating table page 4, 5, 6, 7 & 10 removed i-temp footnote from tables page 5 added i-temp 25ns power numbers to the dc electrical characteristics table dc electrical parameters?changed wording from "open" to "disabled" page 5 & 6 changed transition measurement from 200mv to 0mv in footnotes page 6, 7, 10, & 12 added i-temp to all ac electrical characteristics table page 8 updated timing waveform of write cycle no. 1, r/ w controlled timing page 1 & 17 replaced old idt tm logo with new idt tm logo page 17 added i-temp to 25ns speed grade in ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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